1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and, more particularly, to MOSFETs that achieve improved carrier mobility through the incorporation of strained silicon.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a cross sectional view of a conventional MOSFET device. The MOSFET is fabricated on a silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of a gate 14 and a channel region 16 that are separated by a thin gate insulator 18 such as silicon oxide or silicon oxynitride. A voltage applied to the gate 14 controls the creation of an inversion layer that provides carriers for conduction in the channel region 16 between source and drain regions. To minimize the resistance of the gate 14, the gate 14 is typically formed of a heavily doped semiconductor material such as polysilicon.
The source and drain regions of the MOSFET comprise deep source and drain regions 20 formed on opposing sides of the channel region 16. The deep source and drain regions 20 are formed by ion implantation subsequent to the formation of a spacer 22 around the gate 14. The spacer 22 serves as a mask during implantation to define the lateral positions of the deep source and drain regions 20 relative to the channel region 16.
The source and drain regions of the MOSFET further comprise shallow source and drain extensions 24. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions 24 rather than deep source and drain regions near the ends of the channel 16 helps to reduce short channel effects. The shallow source and drain extensions 24 are implanted after the formation of a protective layer 26 around the gate 14 and over the substrate, and prior to the formation of the spacer 22. The gate 14 and the protective layer 26 act as an implantation mask to define the lateral position of the shallow source and drain extensions 24 relative to the channel region 16. Diffusion during subsequent annealing causes the shallow source and drain extensions 24 to extend slightly beneath the gate 14.
Source and drain silicides 28 are formed on the deep source and drain regions 20 to provide ohmic contacts and reduce contact resistance. The suicides 28 are comprised of the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni). The deep source and drain regions 20 are formed deeply enough to extend beyond the depth to which the source and drain suicides 28 are formed. The gate 14 likewise has a silicide 30 formed on its upper surface. A gate structure comprising a polysilicon material and an overlying silicide as shown in FIG. 1 is sometimes referred to as a polycide gate.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice because of the presence of the larger germanium atoms in the lattice. Since the atoms of the silicon lattice align with the more widely spaced silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET incorporating a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10. An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 24, a gate oxide layer 18, a gate 14 surrounded by a protective layer 26, a spacer 22, source and drain silicides 28, a gate silicide 30, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
An alternative to the formation of devices on semiconductor substrates is silicon on insulator (SOI) construction. In SOI construction, MOSFETs are formed on a substrate that includes a layer of a dielectric material beneath the MOSFET active regions. SOI devices have a number of advantages over devices formed in a semiconductor substrate, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
FIG. 3 shows an example of a strained silicon MOSFET formed on an SOI substrate. In this example, the MOSFET is formed on an SOI substrate that comprises a silicon germanium layer 32 provided on a dielectric layer 36. The MOSFET is formed within an active region defined by trench isolations 12 that extend through the silicon germanium layer 32 to the underlying dielectric layer 36. The SOI substrate may be formed by a buried oxide (BOX) method or by a wafer bonding method. In one alternative to the SOI construction shown in FIG. 3, strained silicon FinFETs comprised of monolithic silicon germanium FinFET bodies having strained silicon grown thereon may be patterned from the silicon germanium layer of the SOI substrate.
FIGS. 4a–4d show structures formed in accordance with a wafer bonding method. FIG. 4a shows a substrate that includes a planarized layer of silicon germanium 38. The silicon germanium is typically grown on a silicon wafer (not shown). The silicon germanium 38 is implanted with hydrogen 40 to form a hydrogen rich region 42 within the silicon germanium material. The hydrogen 40 is implanted with an energy such that the amount of silicon remaining above the hydrogen rich region exceeds the thickness of the silicon germanium layer to be formed on the SOI substrate. In some applications a different material such as oxygen may be implanted. FIG. 4b shows the silicon germanium layer 38 of FIG. 4a after being cleaned, stripped of oxide in a diluted HF solution, rinsed in deionized water to form an active native oxide on its surface, and then inverted and bonded to a planarized oxide layer 46 formed on a semiconductor layer 48 of a second substrate 44. To facilitate bonding, adjoining surfaces of the substrates are planarized to a homogeneity of 0.5 microns or less.
Bonding is generally performed in two stages. In a first stage, the substrates are heated to approximately 600 degrees C. in an inert environment for approximately three hours. As shown in FIG. 4c, the heating of the first stage causes bonding of the silicon germanium layer 38 to the dielectric layer 46 of the second substrate 44 due to Van der Waals forces. The heating of the first stage also causes the silicon germanium layer 38 to fracture in the hydrogen rich region 42. After the first heating stage the fractured portion of the silicon germanium layer may be removed, leaving a new substrate comprising a silicon germanium layer 50 bonded to an oxide layer 46, and having a residual hydrogen rich region 42 at its upper surface. In a second stage of the bonding process, the bonded structure is heated to approximately 1050–1200 degrees C. for 30 minutes to two hours to strengthen the bond between the dielectric layer 46 and the silicon germanium layer 50. The resulting substrate is then planarized and cleaned, leaving a silicon germanium SOI substrate as shown in FIG. 4d. 
One problem with conventional strained silicon devices is that growth of the strained silicon layer on the substrate prior to formation of MOSFET elements causes a significant amount of the strained silicon to be consumed during subsequent processing. Another problem is the formation of “misfit dislocations” in the strained silicon that effectively release the strain applied to the silicon lattice. Misfit dislocations are primarily caused by mismatches between the strained silicon lattice and the lattice of the underlying silicon germanium supporting layer. The amount of misfit dislocations in a strained silicon layer may be increased as the result of thermal factors. One instance in which misfit dislocations may be caused by thermal factors is during cooling after deposition of a strained silicon layer. Another instance in which misfit dislocations may occur is during exposure to high temperatures, e.g. 1000 degrees C. and higher, which are often employed for forming elements such as shallow trench isolations. Such high temperatures are believed to cause depletion of the germanium content of the silicon germanium substrate, leading to formation of misfit dislocations in the overlying strained silicon. The rate of formation of misfit dislocations rises exponentially with increases in temperature.
It has been determined that a strained silicon layer has a critical thickness, above which misfit dislocations become significantly more likely to occur. The critical thickness depends on the amount of tensile strain applied to the silicon lattice, and thus on the germanium content of the underlying silicon germanium layer. For example, it has been determined that a silicon germanium layer having approximately 20% germanium content can support a critical thickness of approximately 200 Angstroms without the risk of significant misfit dislocations, whereas a silicon germanium layer having approximately 30% germanium content can support a critical thickness of only approximately 80 Angstroms.
Therefore the application of current strained silicon technology to MOSFET design is constrained by conflicting limitations, in that strained silicon carrier mobility is enhanced by an increase in the germanium content of the underlying layer, yet the critical thickness of the strained silicon is reduced by an increase of the germanium content of the underlying layer. These conflicts make practical applications difficult to achieve. For example, it has been determined empirically that at least approximately 70 Angstroms of strained silicon are required to provide a meaningful improvement in MOSFET performance. However, in order to account for consumption of silicon during conventional processing, a layer of approximately double that thickness must be formed initially, and to avoid misfit dislocation in a layer of such thickness, the germanium content of the underlying layer must be restricted to approximately 20%. The resulting strain applied to the strained silicon layer has been found to have relatively little effect on hole mobility, and therefore it is difficult to provide a meaningful application of strained silicon in PMOS devices. In addition to the foregoing considerations, the tensile strain of the strained silicon layer and hence its carrier mobility may be further degraded through the formation of misfit dislocations caused by both the increases and the decreases in temperature that are typically encountered during processing, such as during formation of shallow trench isolations. Therefore, while the limiting factors of strained silicon technology can be balanced to achieve limited carrier mobility enhancement in some applications, current technology does not offer a way to impart enough strain to produce significant carrier mobility enhancement without also introducing mobility-reducing defects and strain relaxation.
An additional complication of strained silicon technology is that it is difficult to form fully depleted SOI devices with strained silicon channels. Fully depleted SOI MOSFETs are preferably implemented as devices in which the thickness of the semiconductor material in the channel region is less than the thickness of the depletion region. However, given the need to provide a supporting layer of silicon germanium beneath the strained silicon channel, the total channel thickness becomes greater than that of the depletion region, or the thickness of strained silicon is not sufficient to provide significant mobility enhancement.